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r virtex-ii pro ML324 and ml325 platform user guide ug063 (v1.2) may 30, 2006 p/n 0402276-03
virtex-ii pro ML324 and ml325 platform www.xilinx.com ug063 (v1.2) may 30, 2006 xilinx is disclosing this document and intellectual property (hereinafter ?the design?) to you for use in the development of de signs to operate on, or interface with xilinx fpgas. except as stated herein, none of the design may be copied, reproduced, distributed, republi shed, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical , photocopying, recording, or otherwise, without the prior written consent of xilinx. any unauthorized use of the design may viol ate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. xilinx does not assume any liability arising out of the application or use of the design; nor does xilinx convey any license un der its patents, copyrights, or any rights of others. you are responsible for obtaining any rights you may require for your use or implementatio n of the design. xilinx reserves the right to make changes, at any time, to the design as deemed desirable in the sole discretion of xilinx. xil inx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. xilinx will not assume an y liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the design. the design is provided ?as is? with all faults, and the entire risk as to its function and implementation is with you. you acknowledge and agr ee that you have not relied on any oral or written information or advice, whether given by xilinx, or its agents or employees. xilinx makes no other warranties, whether express, implied, or statutory, re garding the design, including any warranties of merchantability, fitness for a particular purpose, title, and no ninfringement of third-party rights. in no event will xilinx be liable for an y consequential, indirect, exemplary, special, or incidental damages, including any lost data and lost pr ofits, arising from or relating to your use of the design, even if you have been advised of the possibility of such damages. th e total cumulative liability of xilinx in connection with your use of the design, whether in contract or tort or otherwise, will in no event exceed the amount of fees paid by you to xilinx hereunder for use of the design. you acknowledge that the fees, if any, reflect the allocation of ri sk set forth in this agreement and that xilinx would not make available the design to you without th ese limitations of liability. the design is not designed or intended for use in the development of on-line control equipment in hazardous environments requir ing fail- safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic contr ol, life support, or weapons systems (?high-risk applications?). xilinx specifically disclaims any express or implied warranties of fitness for such high-risk applications. you represent that use of the design in such high-risk applications is fully at your risk. ? 2004-2006 xilinx, inc. all rights reserved. xilinx, the xilinx logo, and other designated brands included herein are trademar ks of xilinx, inc. all other trademarks are the property of their respective owners. revision history the following table shows the revision history for this document. date version revision 06/07/04 1.0 initial xilinx release. 05/24/06 1.1 corrected pin numbers in table 7, page 14 . added revision number extensionto p/n on title page. 05/30/06 1.2 updated ?about this guide.? r
virtex-ii pro ML324 and ml325 platform www.xilinx.com 3 ug063 (v1.2) may 30, 2006 preface: about this guide guide contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 additional resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 online document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 virtex-ii pro ML324 and ml325 platform package contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 cd-rom contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1. power switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2. power supply jacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3. fpga configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4. oscillator sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. single-ended sma clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. differential oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7. differential sma clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8. user leds (active high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9. user dip switches (active high). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10. user push buttons (active high) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 11. bert headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 12. recovered clock monitor headers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 13. program switch (active low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 14. reset switch (active low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15. done led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 16. init led . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 17. config address dip switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 18. rocketio transceiver pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 19. rs-232 port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 20. sdram connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table of contents
4 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 r
virtex-ii pro ML324 and ml325 platform www.xilinx.com 5 ug063 (v1.2) may 30, 2006 r preface about this guide this document describes the features and operation of the virtex?-ii pro ML324 and ml325 prototype and demonstration boards. guide contents this manual contains the following chapter: ? ?virtex-ii pro ML324 and ml325 platform? additional resources to find additional documentation, see the xilinx website at: http://www.xilinx.com/literature . to search the answer database of silicon, software, and ip questions and answers, or to create a technical support webcase, see the xilinx website at: http://www.xilinx.com/support . conventions this document uses the following conventions. an example illustrates each convention. typographical the following typographical conventions are used in this document: convention meaning or use example courier font messages, prompts, and program files that the system displays speed grade: - 100 courier bold literal commands that you enter in a syntactical statement ngdbuild design_name helvetica bold commands that you select from a menu file open keyboard shortcuts ctrl+c
6 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 preface: about this guide r online document the following conventions are used in this document: italic font variables in a syntax statement for which you must supply values ngdbuild design_name references to other manuals see the development system reference guide for more information. emphasis in text if a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. square brackets [ ] an optional entry or parameter. however, in bus specifications, such as bus[7:0] , they are required. ngdbuild [ option_name ] design_name braces { } a list of items from which you must choose one or more lowpwr = { on | off } vertical bar | separates items in a list of choices lowpwr = { on | off } vertical ellipsis . . . repetitive material that has been omitted iob #1: name = qout? iob #2: name = clkin? . . . horizontal ellipsis . . . repetitive material that has been omitted allow block block_name loc1 loc2 ... locn; convention meaning or use example convention meaning or use example blue text cross-reference link to a location in the current document see the section ?additional resources? for details. refer to ?title formats? in chapter 1 for details. red text cross-reference link to a location in another document see figure 2-5 in the virtex-ii platform fpga user guide. blue, underlined text hyperlink to a website (url) go to http://www.xilinx.com for the latest speed files.
virtex-ii pro ML324 and ml325 platform www.xilinx.com 7 ug063 (v1.2) may 30, 2006 r virtex-ii pro ML324 and ml325 platform package contents ? xilinx virtex?-ii pro ML324 or ml325 platform (referred to as the ?ml32x platform?) ? user guide ? four sma-to-sma coax cable assemblies ? cd-rom ? compactflash (cf) memory for system ace? solution ? rs-232 cable ? power supply cd-rom contents ? user guide in pdf format ? example design file for demonstration of the rocketio? transceivers ? system ace files ( *.ace ) for each part type supported by the board ? full schematics of the board in both pdf format and viewdraw schematic format ? pc board layout in pads pcb format ? gerber files in *.pho and *.pdf for the pc board (there are many free or shareware gerber file viewers available on the internet for viewing and printing these files)
8 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 conventions r conventions the voltage range names used on the ml32 x platform differs from those shown in the virtex-ii pro platform fpgas: complete data sheet (ds083) at http://direct.xilinx.com/bvdocs/publications/ds083.pdf they correspond as shown in table 1 : introduction the ml32 x platform allows designers to investigate and experiment with the features of rocketio transceivers. this document describes the features and operation of the boards. the platforms and their corresponding packages are shown in table 2 . features ? virtex-ii pro fpga ? on-board power supplies for all necessar y voltages capable of supplying 3a each ? power supply jacks for optional use of external power supplies ? jtag configuration port for use with parallel cable iii and parallel cable iv cables ? system ace configuration controller ? rs-232 serial port ? two 125-mhz or 156.25-mhz differential clock oscillators ? two 2.5v clock oscillator sockets ? four differential clock pairs with sma connectors ? two single-ended clocks with sma connectors ? one pair of 36-position headers with ground headers for parallel bert cables ? 16 or 32 pairs of sma connectors for the rocketio transceivers ? power indicator leds ? general purpose dip switches, leds, and push buttons ? 128 mb sdram table 1: voltage range names data book board data book board vccaux vaux vcco vcco vccauxrx avccaux vtrx vt_rx vccauxtx avccaux vttx vt_tx vccint vcore table 2: platforms and packages platform package ML324 ff1517 ml325 ff1704
virtex-ii pro ML324 and ml325 platform www.xilinx.com 9 ug063 (v1.2) may 30, 2006 introduction r figure 1 shows a block diagram of the board. figure 1: virtex-ii pro ml32 x platform block diagram * header s recovered clock s bert 2 x 3 6 bert 3 x 3 6 led s gp s w s pb s w 3 pb s w 4 diff clock s right angle s ma mgt mgt o s c s ma o s c s ocket s ma 2 x 2 diff o s c * header s recovered clock s diff clock s right angle s ma right angle s ma right angle s ma program mgt mgt s y s tem ace s ol u tion uart rx tx done led init led led s gp s w s pb s w 1 pb s w 2 power bu s and switche s 5v j a ck 5v brick -or- vcc j a ck vcco j a ck aux j a ck j a ck mgt j a ck vcore 1.5v vcco 2.5v vccaux 2.5v mgt aux 2.5v vcc 3 3 . 3 v tx top j a ck tx top 1.8v - 2.5v rx top j a ck rx top 1.8v - 2.5v tx bot j a ck tx bot 1.8v - 2.5v rx bot j a ck rx bot 1.8v - 2.5v ug06 3 _01_042706 virtex-ii pro fpga * headers 8 in ff1517 10 in ff1704 * mgt 4 x 4 in ff1517 4 x 5 in ff1704 launch sma active high active high 128 m b s dram o s c s ma o s c s ocket s ma 2 x 2 diff o s c
10 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 detailed description r detailed description the ml325 platform show in n figure 2 represents the ml32x platforms described in this user guide. each feature is detailed in the numbered sections that follow. figure 2: detailed description of virtex-ii pro ml32 x platform components 4 18 7 19 11 5 2 1 17 13 16 15 6 6 14 7 7 8 8 9 9 10 12 12 3 20 ug063_02_042706
virtex-ii pro ML324 and ml325 platform www.xilinx.com 11 ug063 (v1.2) may 30, 2006 detailed description r 1. power switch the board has an on-board power supply and an on|off power switch. when lit, a green led indicates power from the power brick connector or the 5v jack. on position in the on position, the power switch enables deliver y of all power to the board by way of voltage regulators situated close to the left and right edges of the board. these regulators feed off a 5v external power brick or the 5v power supply jack. the voltage regulators deliver fixed voltag es. maximum current range for each voltage regulator is 3a. rocketio termination voltages are situated on the right edge of the board and are marked as vt_rx, vt_tx (top set) and vt_rx, vt_tx (bottom set). these can be used to deliver a fixed voltage by appropriate selection of the resistors designated as r32, r39, r46, and r49 (default is set to 2.5v). these can be made to deliver a variable voltage by depopulating the above mentioned resistors and manipulating the potentiometers (r3, r9, r10, r11). the voltage range is as shown in table 3 . off position in the off position, the power switch disables all modes of powering the fpga. power enable jumpers for each power supply there are headers marked supply on one side and jack on the other side. appropriate placements of jumpers on these headers enables delivery of all power from either the on-board regulators or power supply jacks marked v5, vcore, vcco, vccaux, avccaux, vt_tx, vt_rx (top set) and vt_tx, vt_rx (bottom set). table 3: voltage ranges label max voltage vcore 1.5v (1.65v for -es devices) vcco 2.5v vccaux 2.5v avccaux 2.5v vt_tx (top set) 1.7 - 2.5v vt_rx (top set) 1.7 - 2.5v vt_tx (bottom set) 1.7 - 2.5v vt_rx (bottom set) 1.7 - 2.5v
12 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 detailed description r 2. power supply jacks one method of delivering power to the fpga is by way of the power supply jacks. these jacks are: ? avccaux ? supplies power to the rocketio transceivers on the fpga ? vccaux ? supplies voltage to the v aux header and the v aux fpga pins ? vcco ? supplies i/o voltages to the fpga ? vcore ? supplies voltage to the core of the fpga (consult the virtex-ii pro platform fpgas: complete data sheet (ds083) at http://direct.xilinx.com/bvdocs/publications/ds083.pdf for the maximum vcore voltage for the device you are using) the following two jacks supply termination volt ages to the rocketio transceivers on the top and bottom edges of the fpga: ? vt_tx (top set and bottom set) ? vt_rx (top set and bottom set) note: 5v must always be applied to the 5v jack or to the external power brick connector to power the 3.3v regulator for the system ace chip. 3. fpga configuration the fpga can only be configured in jtag mode using one of the following options: ? parallel cable iii cable ? parallel cable iv cable ? system ace configuration controller (1) using the configuration address dip switches, one of eight bitstreams stored in the compactflash memory can be accessed through the on-board system ace controller. note: when using the flying wire leads or the parallel cable iv cable, the system ace controller will be bypassed, thus causing no disruption in the jtag chain. 1. for further information, consult the system ace compactflash solution (ds080) http://www.xilinx.com/bvdocs/publications/ds080.pdf .).
virtex-ii pro ML324 and ml325 platform www.xilinx.com 13 ug063 (v1.2) may 30, 2006 detailed description r 4. oscillator sockets the ml32 x platform has two crystal oscillator sockets, each wired for standard lvttl-type oscillators. these connect to the fpga clock pins as shown in table 4 . the oscillator sockets accept both half- and full-sized oscillators and are powered by 3.3v or the vcco 2.5v power supply. 5. single-ended sma clocks the ml32 x platform has two sma clock inputs that allow connection to an external function generator. these connect to the fpga clock pins as shown in table 5 . table 4: o s c connections label ML324 ml325 clock name pin clock name pin x3 clk_ocs_top m21 clk_ocs_top j22 x5 clk_ocs_bot ag20 clk_ocs_bot ap21 table 5: s ma clock pin connections label ML324 ml325 clock name pin clock name pin j27 clk_sma_top l21 clk_sma_top k22 j43 clk_sma_bot ah20 clk_sma_bot an21
14 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 detailed description r 6. differential oscillators the ml32 x platform has two differential oscillato rs, each wired to lvds inputs on the fpga. these connect to the fpga clock pins shown in table 6 . the differential oscillators are powered by 3.3v or the vcco 2.5v power supply. 7. differential sma clock there are four pairs of 50 sma connectors that can be used (with 100 termination) to connect to an external function generator. these connect to the fpga pins as shown in table 7 . these sma connectors can also be used as eight single-ended clock inputs. table 6: differential oscillator pin connections label ML324 ml325 clock name pin clock name pin x2 clk_bref2_top_p clk_bref2_top_n k20 j20 clk_bref2_top_p clk_bref2_top_n g21 f21 x4 clk_bref_bot_p clk_bref_bot_n at20 ar20 clk_bref_bot_p clk_bref_bot_n au22 at22 table 7: differential clock pin connections label ML324 ml325 clock name pin clock name pin j21 j23 clk_bref_top_p clk_bref_top_n e20 d20 clk_bref_top_p clk_bref_top_n g22 f22 j41 j42 clk_bref2_bot_p clk_bref2_bot_n ak20 al20 clk_bref2_bot_p clk_bref2_bot_n at21 au21 j16 j19 clk_diff_top_p clk_diff_top_n m20 n20 clk_diff_top_p clk_diff_top_n k21 j21 j47 j48 clk_diff_bot_p clk_diff_bot_n aj21 ah21 clk_diff_bot_p clk_diff_bot_n an22 ap22
virtex-ii pro ML324 and ml325 platform www.xilinx.com 15 ug063 (v1.2) may 30, 2006 detailed description r 8 . user leds (active high) there are 20 active-high leds, as shown in table 8 and table 9 , connected to user i/o pins on the fpga. these leds can be used to indicate status or for any other purpose the user desires. table 8: user leds - led row 1 led row 1 ML324 ml325 pin pin ds15 ak30 at10 ds13 al30 av10 ds12 an30 aw10 ds11 am30 ar11 ds10 at30 ap11 ds9 al29 av11 ds8 at29 au11 ds14 am29 ay10 ds26 ar29 ay11 ds27 ak29 an12 table 9: user leds - led row 2 led row 2 ML324 ml325 pin pin ds29 d10 ab7 ds28 h14 ab9 ds23 e15 ab10 ds16 g15 ac3 ds17 f14 ac4 ds18 d14 ac11 ds19 j10 a12 ds20 g11 ac6 ds21 f10 ac7 ds22 e11 ac9
16 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 detailed description r 9. user dip switches (active high) there are 20 active-high dip switches, as shown in table 10 and table 11 , connected to user i/o pins on the fpga. these dip switches can be used to generate vectors or any other purpose that the user sees fit. table 10: user dip s witches - s w1 s w1 ML324 ml325 pin pin 1aa10 am2 2ab10 ap2 3ac10 ar2 4ad10 at2 5ae10 au2 6af10 av2 7ag10 aw2 8ah10 ad1 9ab11 ae1 10 af11 af1 table 11: user dip s witches - s w2 s w2 ML324 ml325 pin pin 1m10 ah1 2n10 aj1 3p10 ak1 4r10 am1 5t10 an1 6u10 ap1 7v10 at1 8w10 au1 9n11 av1 10 t11 aw1
virtex-ii pro ML324 and ml325 platform www.xilinx.com 17 ug063 (v1.2) may 30, 2006 detailed description r 10. user push buttons (active high) there are four active-high push buttons, as shown in table 12 , connected to user i/o pins on the fpga. these push buttons can be used for any purpose that the user sees fit. 11. bert headers there is one pair of 72-position headers intended to be used for parallel bit error rate testing (bert). the odd numbered pins of the bert headers j56 and j55 are connected to user i/o pins (see table 13 , which spans multiple pages). the even numbered pins of j56 and j55 are connected to gnd. the third row of header pins (j49) to the left of j55 are connected to vcco. this gives the user the ability to jumper i/o pins on j56 to gnd and i/o pins on j55 to either vcco or gnd. table 12: user push buttons label ML324 ml325 pin pin sw7 d30 g33 sw6 e30 f33 sw3 al18 d34 sw8 ak18 c34 table 13: bert headers j56 and j55 header j56 ML324 ml325 polarity header j55 ML324 ml325 polarity pin pin pin pin 1h34d42 n1ab35ab37n 2h33d41 p3ab34ab36 p 3h38e42 n5ab37ad38n 4 h37 e41 p 7 ab36 ad37 p 5j39f42 n9ac39af40 n 6 j38 f41 p 11 ac38 af39 p 7 k33 g41 n 13 ad34 ag37 n 8 k34 g42 p 15 ad33 ag38 p 9 k39 j42 n 17 ad38 ak40 n 10 k38 j41 p 19 ad37 ak39 p 11 l37 k41 n 21 ae37 ak36 n 12 l36 k42 p 23 ae36 ak35 p 13 l39 l42 n 25 ae39 am39 n 14 l38 l41 p 27 ae38 am38 p 15 m34 n42 n 29 af34 ap39 n 16 m33 n41 p 31 af33 ap38 p
18 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 detailed description r 17 n39 r42 n 33 af39 at38 n 18 n38 r41 p 35 af38 ar37 p 19 p36 g38 n 37 ag34 ah42 n 20 p35 h37 p 39 ag33 ah41 p 21 p39 j38 n 41 ah38 ak42 n 22 p38 j39 p 43 ah37 ak41 p 23 r35 l38 n 45 aj37 am42 n 24 r34 l39 p 47 aj36 am41 p 25 r39 m36 n 49 aj35 an42 n 26 r38 m35 p 51 aj34 an41 p 27 t38 n40 n 53 aj39 ap42 n 28 t37 n39 p 55 aj38 ap41 p 29 u35 r38 n 57 ak36 at42 n 30 u34 r37 p 59 ak35 at41 p 31 v35 u40 n 61 ak39 au42 n 32 v34 u39 p 63 ak38 au41 p 33 v37 w38 n 65 al34 av42 n 34 v36 w37 p 67 al33 av41 p 35 w35 aa37 n 69 al39 aw42 n 36 w34 aa36 p 71 al38 aw41 p table 13: bert headers j56 and j55 (continued) header j56 ML324 ml325 polarity header j55 ML324 ml325 polarity pin pin pin pin
virtex-ii pro ML324 and ml325 platform www.xilinx.com 19 ug063 (v1.2) may 30, 2006 detailed description r 12. recovered clock monitor headers there are 16 or 20 2-pin headers connected to user i/o pins near the top and bottom of the fpga. these headers are intended to be used to monitor the recovered clock for each rocketio transceiver as shown in table 14 . note, if these headers are not being used to monitor the clocks, they may be used for any other purpose the user sees fit. table 14: recovered clock monitor pins label ML324 ml325 pin pin j136 c11 c11 j135 d11 c15 j53 k13 j10 c14 f19 j30 c15 m21 j12 c22 h23 j39 c23 d24 j96 c29 l27 j50 f30 j134 c30 g31 j13 au10 at12 j54 at13 j28 au11 ay15 j140 au14 aw19 j139 au15 av20 j137 au22 ar23 j138 au23 ay24 j20 au29 ay28 j141 au30 j11 au30 an31
20 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 detailed description r 13. program switch (active low) the active-low program switch, when pressed, grounds the program pin on the fpga. 14. reset switch (active low) the active-low reset switch resets the system ace controller. 15. done led the done led indicates the status of the done pin on the fpga. this led lights when done is high or if power is applied to the board without a part in the socket. 16. init led the init led lights during initialization. 17. config address dip switch this switch (sw5) is used to select one of eight addresses in the compactflash memory card, from which a configuration bitstream can be read. the open (?o?) position indicates a logic ?0? and the closed (?c?) position indicates a logic ?1? as shown in table 15 . table 15: bitstream address table 210addr ooo 0 ooc 1 oco 2 occ 3 coo 4 coc 5 cco6 ccc 7
virtex-ii pro ML324 and ml325 platform www.xilinx.com 21 ug063 (v1.2) may 30, 2006 detailed description r 1 8 . rocketio transceiver pins the rocketio transceiver pins are as shown in table 16 . table 16: rocketio tx and rx pin pairs mgt ML324 ml325 txp txn rxp rxn txp txn rxp rxn 2 a35 a36 a34 a33 a40 a41 a39 a38 3 a36 a37 a35 a34 4 a31 a32 a30 a29 a32 a33 a31 a30 5 a27 a28 a26 a25 a28 a29 a27 a26 6 a23 a24 a22 a21 a24 a25 a23 a22 7 a18 a19 a17 a16 a20 a21 a19 a18 8 a14 a15 a13 a12 a16 a17 a15 a14 9 a10 a11 a9 a8 a12 a13 a11 a10 10 a8 a9 a7 a6 11 a6 a7 a5 a4 a4 a5 a3 a2 14 aw6 aw7 aw5 aw4 bb4 bb5 bb3 bb2 15 bb8 bb9 bb7 bb6 16 aw10 aw11 aw9 aw8 bb12 bb13 bb11 bb10 17 aw14 aw15 aw13 aw12 bb16 bb17 bb15 bb14 18 aw18 aw19 aw17 aw16 bb20 bb21 bb19 bb18 19 aw23 aw24 aw22 aw21 bb24 bb25 bb23 bb22 20 aw27 aw28 aw26 aw25 bb28 bb29 bb27 bb26 21 aw31 aw32 aw30 aw29 bb32 bb33 bb31 bb30 22 bb36 bb37 bb35 bb34 23 aw35 aw36 aw34 aw33 bb40 bb41 bb39 bb38 note: shaded areas denote pins that are not used.
22 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 detailed description r 19. rs-232 port pins the rs-232 port pins are as shown in table 17 . the pins are set up in dte mode as shown in figure 3 . table 17: r s -232 port pins fpga uart port name direction net ML324 ml325 txd out t1in ak25 av34 rts out t2in ap26 au34 rxd in r1out ar26 ar34 cts in r2out am25 at34 figure 3: r s -232 pins in dte mode ug063_03_042506 rs-232 db9 virtex-ii pro u1 u2 j52 t1in txd rts rxd cts pin 3 pin 7 pin 2 pin 8 t2in r1out r2out
virtex-ii pro ML324 and ml325 platform www.xilinx.com 23 ug063 (v1.2) may 30, 2006 detailed description r 20. sdram connection the ml32x platform has 128mb sdram on-board memory, micron part number mt48v4m32lffc-8. the connections to the virtex-ii pro fpga are shown in table 18 (which spans multiple pages). table 18: headers for the s dram s ignals ML324 ml325 ML324 ml325 pin name pin pin pin name pin pin r9 dq2 ae1 r1 a1 dq26 k2 f1 r8 dqo ae2 r2 a2 dq24 l1 f2 r7 vdd4 vcco vcco a3 vss1 gnd gnd r3 vss4 gnd gnd a7 vdd1 vcco vcco r2 dq15 aj1 v2 a8 dq23 l3 j2 r1 dq13 aj2 w1 a9 dq21 m3 k1 p9 dq4 ad2 p2 b1 dq28 k1 e2 p8 vssq11 filtered gnd filtered gnd b2 vddq1 filtered vcco filtered vcco p7 vddq11 filtered vcco filtered vcco b3 vssq1 filtered gnd filtered gnd p3 vssq10 filtered gnd filtered gnd b7 vddq2 filtered vcco filtered vcco p2 vddq10 filtered vcco filtered vcco b8 vssq2 filtered gnd filtered gnd p1 dq11 ak1 w2 b9 dq19 r2 k2 n9 vddq9 filtered vcco filtered vcco c1 vssq3 filtered gnd filtered gnd n8 dq3 ac2 p1 c2 dq27 j1 e1 n7 dq1 af1 t2 c3 dq25 l2 g1 n3 dq14 ah2 v1 c7 dq22 k3 j1 n2 dq12 ak2 y3 c8 dq20 t2 l1 n1 vssq9 filtered gnd filtered gnd c9 vddq3 filtered vcco filtered vcco m9 vddq8 filtered vcco filtered vcco d1 vssq4 filtered gnd filtered gnd m8 dq5 ac1 n2 d2 dq29 j2 d2 m7 dq6 af2 u1 d3 dq30 n1 g2 m3 dq9 ag2 u2 d7 dq17 j3 h2 m2 dq10 al1 y4 d8 dq18 u2 l2
24 www.xilinx.com virtex-ii pro ML324 and ml325 platform ug063 (v1.2) may 30, 2006 detailed description r note: 1. for proper operation of the sdram, use the lvcmosdci25 voltage standard on the fpga pins. 2. cs# is tied to the jumper labeled ram_enable/ram_disable. 3. disable the sdram when using the dut pins as standard i/o pins. 4. for information on sdram operation, see: http://www.micron.com/products/dram/sdram/ document status refers to the internal classi fication of the document . this classification can affect how and to whom the document is distributed. m1 vssq8 filtered gnd filtered gnd d9 vddq4 filtered vcco filtered vcco l9 vssq7 filtered gnd filtered gnd e1 vddq5 filtered vcco filtered vcco l8 dq7 ab2 n1 e2 dq31 h2 d1 l7 vdd3 vcco vcco e3 nc1 nc nc l3 vss3 gnd gnd e7 nc2 nc nc l2 dq8 al2 aa3 e8 dq16 v2 m2 l1 vddq6 filtered vcco filtered vcco e9 vssq5 filtered gnd filtered gnd k9 dqm0 ah3 e3 f1 vss2 gnd gnd k8 we# ag3 f3 f2 dqm3 p1 u3 k7 cas# af3 g3 f3 a3 n2 d3 k3 nc5ncncf7 a2 p2 g4 k2 nc4ncncf8 dqm2r1 h4 k1 dqm1 ae3 h3 f9 vdd2 vcco vcco j9 ras# ad3 k3 g1 a4 p3 j4 j8 cs# header j49 header j166 g2 a5 n3 l4 j7 ba0 ab4 l3 g3 a6 r3 m4 j3 a9 ab3 m3 g7 a10 t3 n4 j2 cke aa4 n3 g8 a0 u4 t4 j1 clk ag20 ap21 g9 a1 v3 u4 h9 nc/a11 y3 p3 h1 a7 v4 v4 h8 ba1w4r3 h2 a8 w3w3 h7 nc/a12 nc t3 h3 nc3 nc nc table 18: headers for the s dram s ignals (continued) ML324 ml325 ML324 ml325 pin name pin pin pin name pin pin

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